p1708c notebook lcd panel emi reduction ic ?2010 scillc. all rights reserved. publication order number: february 2010 C rev. 2 p1708/d features fcc approved method of emi attenuation. generates a low emi spread spectrum clock of the input frequency. optimized for frequency range from 50 to 110mhz. internal loop filter minimizes external components and board space. four selectable spread ranges. low inherent cycle-to-cycle jitter. 3.3v operating voltage range. ttl or cmos compatible inputs and outputs. cmos design. o 8.46ma @ 3.3v, 54mhz o 9.79ma @ 3.3v, 65mhz o 12.06ma @ 3.3v, 81mhz o 16.51ma @ 3.3v, 108mhz supports notebook vga and other lcd timing controller applications. pinout compatible to ics mk1708 and cypress cy25560. sson / sbm pin for spread spectrum on/off and standby mode controls. available in 8-pin soic and tssop. product description the p1708c is a versatile spread spectrum frequency modulator designed specifically for input clock fre quencies. the p1708c reduces electromagnetic interference (em i) at the clock source, allowing system wide reduction of emi of down stream clock and data dependent signals. the p1708c allows significant system cost savings by re ducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass emi regulations. the p1708c modulates the output of a single pll in order to spread the bandwidth of a synthesized clock, a nd more importantly, decreases the peak amplitudes of its harmonics. this result in significantly lower syste m emi compared to the typical narrow band signal produced by oscillators and most frequency generators. lowering emi by increasing a signals bandwidth is called sprea d spectrum clock generation. the p1708c uses the most efficient and optimized modulation profile approved by the fcc and is implemented in a proprietary all digital method. applications the p1708c is targeted towards notebook lcd display s, and other displays using an lvds interface, pc peri pheral devices, and embedded systems. block diagram vss clkin feedback divider modulation phase detector loop filter vco output divider modout pll vdd sson sr0 sr1 frequency divider
p1708c rev. 2 | page 2 of 7 | www.onsemi.com sson/sbm pin configuration pin description pin# pin name type description 1 clkin i connect to externally generated clock signal. to pu t the part into standby mode, disable the input clock signal to this pin and pull sson / sbm (pin 5) low. refer to standby mode selection table. 2 vdd p connect to +3.3v. 3 vss p ground connection. connect to system ground . 4 modout o spread spectrum clock output. 5 sson / sbm i spread spectrum on/off and standby mode control. re fer to standby mode selection table. this pin has an internal pull-up resistor. 6 sr1 i digital logic input used to select spreading range. refer to spread spectrum selection table. this pin has an internal pull-up resistor. 7 sr0 i digital logic input used to select spreading range. refer to spread spectrum selection table. this pin has an internal pull-up resistor. 8 nc - no connect. standby mode selection clkin sson / sbm spread spectrum modout pll mode disabled 0 n/a disabled disabled standby disabled 1 n/a disabled free running free running enabled 0 off reference disabled buffer out enabled 1 on normal normal normal 1 2 3 4 5 6 7 8 p1708c clkin vdd vss modout sr1 sr0 nc
p1708c rev. 2 | page 3 of 7 | www.onsemi.com spread range selection sr1 sr0 spreading range modulation rate 0 0 1.00% (f in /40) * 62.49khz 0 1 2.00% (f in /40) * 62.49khz 1 0 0.25% (f in /40) * 62.49khz 1 1 0.75% (f in /40) * 62.49khz schematic for notebook vga application note: to set the p1708c to standby mode, disable th e input clock (pin 1 clkin) and pull sson (pin 5) l ow. refer to standby mode selection table. absolute maximum ratings symbol parameter rating unit vdd, v in voltage on any pin with respect to ground -0.5 to +7.0 v t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114- b) 2 kv note: these are stress ratings only and are not imp lied for functional use. exposure to absolute maxim um ratings for prolonged periods of time may affect device reliability. operating conditions parameter description min max unit vdd supply voltage 2.7 3.7 v t a operating temperature (ambient temperature) -40 + 85 c c l load capacitance 15 pf c in input capacitance 7 pf pin 8 can be tied either high or low, or it can be left unconnected. tie sr0 and sr1 high / low according to spread range desired. external resistors are not needed to pull these pins high. pin 5 sson should be left unconnected to turn on spread spectrum. pull this pin low to turn spread spectrum off and enable stand-by mode. 50mhz to 110mhz pixel clock input from vga chip. fb vdd 0.1f 1 2 4 3 8 7 5 6 clkin vdd vss modout sson sr1 sr0 nc p1708c 50mhz to 110mhz pixel clock input from vga chip.
p1708c rev. 2 | page 4 of 7 | www.onsemi.com dc electrical characteristics symbol parameter min typ max unit v il input low voltage gnd-0.3 0.8 v v ih input high voltage 2.0 v dd +0.3 v i il input low current (pull-up resistors on inputs sr0, sr1 and sson/sbm) -35 a i ih input high current 35 a i xol x out output low current @ 0.4v, v dd = 3.3v 3 ma i xoh x out output high current @ 2.5v, v dd = 3.3v 3 ma v ol output low voltage v dd = 3.3v, i ol = 20ma 0.4 v v oh output high voltage v dd = 3.3v, i oh = 20ma 2.5 v i cc dynamic supply current normal mode 3.3v and 10pf loading 7.90 9.79 17.53 f in -max ma i dd static supply current standby mode 0.6 ma v dd operating voltage 2.7 3.3 3.7 v t on power up time (first locked clock cycle after powe r up) 0.18 ms z out clock output impedance 50 ac electrical characteristics symbol parameter min typ max unit f in input frequency 50 110 mhz f out output frequency 50 110 mhz t lh 1 output rise time measured at 0.8v to 2.0v 0.7 0.9 1.1 ns t h 1 output fall time measured at 0.8v to 2.0v 0.6 0.8 1.0 ns t jc jitter (cycle-to-cycle) 360 ps t d output duty cycle 45 50 55 % note: 1. t lh and t hl are measured into a capacitive load of 15pf.
p1708c rev. 2 | page 5 of 7 | www.onsemi.com package information 8-pin soic package d e h d a1 a2 a q l c b e symbol dimensions inches millimeters min max min max a1 0.004 0.010 0.10 0.25 a 0.053 0.069 1.35 1.75 a2 0.049 0.059 1.25 1.50 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.18 0.25 d 0.193 bsc 4.90 bsc e 0.154 bsc 3.91 bsc e 0.050 bsc 1.27 bsc h 0.236 bsc 6.00 bsc l 0.016 0.050 0.41 1.27 0 8 0 8 note: controlling dimensions are millimeters. soic: 0.074 grams unit weight.
p1708c rev. 2 | page 6 of 7 | www.onsemi.com e h a a1 a2 d b c l q e 8-pin tssop symbol dimensions inches millimeters min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.033 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.028 0.50 0.70 0 8 0 8
p1708c note: this product utilizes us patent #6,646,463 im pedance emulator patent issued to pulsecore semicon ductor, dated 11-11-2003. on semiconductor and are registered trademarks of semiconductor componen ts industries, llc (scillc). scillc reserves the ri ght to make changes without further notice to any products herein. sci llc makes no warranty, representation or guarantee regarding the suitability of its products for any p articular purpose, nor does scillc assume any liability arisi ng out of the application or use of any product or circuit, and specifically disclaims any and all lia bility, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. al l operating parameters, including typicals must b e validated for each customer application by customer 's technical experts. scillc does not convey any l icense under its patent rights nor the rights of ot hers. scillc products are not designed, intended, or auth orized for use as components in systems intended fo r surgical implant into the body, or other applicat ions intended to support or sustain life, or for any oth er application in which the failure of the scillc p roduct could create a situation where personal inju ry or death may occur. should buyer purchase or use scillc pro ducts for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs , damages, and expenses, and reasonable attorney fe es arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use, even if such claim alleges tha t scillc was negligent regarding the design or manufacture o f the part. scillc is an equal opportunity/affirmat ive action employer. u.s patent pending; timing-sa fe and active bead are trademarks of pulsecore semicon ductor, a wholly owned subsidiary of on semiconduct or. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ordering codes part number marking package type temperature p1708cf-08sr aay 8-pin soic, tape and reel, pb free 0c to +70c P1708CF-08TR aay 8-pin tssop, tape and reel, pb fre e 0c to +70c a microdot placed at the end of last row of marki ng or just below the last row toward the center of package indicates pb-free licensed under us patent #5,488,627 and #5,631,921
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